Thursday, May 2025
09:00 AM - 09:20 AM
Room: LL21EF
Session: Artificial Intelligence for Active Matrix Devices
Layout Engineering for Oxide Mura Mitigation in AMOLED Displays: A Data-Driven Causal Analysis
Description:
The development of AMOLED products utilizing the oxide semiconductor HOP has faced challenges due to the occurrence of oxide mura, a reliability issue marked by display non-uniformity. Although changes in oxide properties are hypothesized to result from hydrogen diffusion in the ILD(interlayer dielectric) layer, the exact causes behind the inconsistent occurrence of oxide mura across products with identical process conditions remain an open question. This study investigates the potential causes of oxide mura by analyzing layout changes due to the implementation of BRS (Border Reduction Structure) technology, which was identified as a likely contributing factor. Given the complex correlations and hierarchical relationships among candidate causes, we utilized Graphical Causal Modeling (GCM) to infer causality, providing a robust analysis of distribution changes under varying influences, such as PA process conditions, pixel design layout, product specifications, and operating driving conditions. Our findings enable the prediction of oxide mura risk in new products, identifying critical parameters for modification and offering insights into the simultaneous effects of layout and process conditions. This approach enhances our understanding of the factors influencing oxide semiconductors, facilitating improved product reliability and quality in future AMOLED developments.